1. Field of the Invention
This invention relates to circuit architecture for inputting and outputting serial digital data to and from a parallel data bus. More particularly, this invention relates to circuit architecture capable of interfacing a parallel data bus with a serial bus wherein the same bit registers are used to transmit and receive outbound and inbound data.
2. Description of the Prior Art
Both serial and parallel interfaces are well known to those of ordinary skill in the art. Serial interfaces involve time-sequential processing of the individual parts as a whole, such as the bits of a character, characters of a word, and so on, using the same circuit facilities for processing the successive parts. Parallel interfaces, on the other hand, involve simultaneous processing of individual parts of a whole, using separate facilities for the various parts.
It is often necessary to convert serial data to parallel data and parallel data to serial data so that two apparatus can communicate digitally with one another. Digital Signal Processing (DSP) integrated circuits (ICs), for example, may have an internal parallel bus, but may communicate with other devices or circuitry in a serial data fashion. Therefore, serial to parallel and parallel to serial conversion must be performed so that serial data to and from other devices can be placed on and taken off of the DSP's internal parallel bus. Shift registers are generally used to make these conversions.
For example, a 16-bit serial to parallel port and a 16-bit parallel to serial port would consist of two 16-bit registers. One 16-bit register for the serial to parallel path and one 16-bit register for the parallel to serial path. Using two 16-bit registers for two separate circuits consumes both circuit space and power. Consequently, additional control circuitry must control each serial to parallel and parallel to serial data port so that they operate without locking up the data bus.
Furthermore, in a normal 8-bit serial to parallel and an 8-bit parallel to serial port having buffered 8-bit registers (two 8-bit registers for each parallel to serial and serial to parallel port). One register is used to latch inbound serial data. After the inbound serial data is received, the data is transferred to a buffer register so, for example, the microcode of the DSP IC could extract the data from the register in a parallel fashion. Double buffering mode allows microcode to access data during a later clock cycle. Similarly, a separate transmit or outbound register is used to shift 8-bit parallel data from a parallel bus. The register would buffer the outbound data from, for example, microcode so that the buffered register could hold and transfer the outbound data to an outbound register, which allows the outbound data to be shifted serially at the next timing frame onto the transmit serial bus.
The general 8-bit buffered serial to parallel circuit and parallel to serial circuits require two separate 8-bit registers connected to the parallel bus, one 8-bit register for each circuit. For example, if the parallel bus is internal to a DSP IC and the serial bus is external to the DSP IC, and outbound data is being transferred from the parallel internal bus to the external serial bus and inbound data is being transferred from the external serial bus to the internal parallel bus. Two separate data port circuits are required, one circuit for outbound data and a second circuit for inbound data. Each circuit has its own separate register connected to the internal parallel bus. Thus, circuit space and power are required for each of the inbound and outbound data port circuits.
Furthermore, if an internal parallel bus received and transmitted both linear data and pulse code modulated (PCM) data wherein the linear data is 16-bit data and the PCM data is 8-bit, according to the above discussion, four separate circuits would be required. One for inbound serial to parallel 16-bit linear data, a second for outbound parallel to serial 16-bit linear data, a third for inbound serial to parallel PCM 8-bit data, and a fourth for outbound parallel to serial PCM 8-bit data. The four separate circuits would each require circuitry space and power if all are placed within an electronic apparatus and, in particular, a DSP IC.
Thus, the above discussed normal architectures for inbound and outbound data are disadvantageous because they all require their own circuitry and power, they are not combined into a single circuit capable of handling both inbound and outbound n-bit linear data as well as inbound and outbound m-bit PCM data (where m.ltoreq.n).